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      首頁(yè)編程開(kāi)發(fā)其它知識(shí) → Proteus仿真速度很慢的分析

      Proteus仿真速度很慢的分析

      相關(guān)軟件相關(guān)文章發(fā)表評(píng)論 來(lái)源:本站整理時(shí)間:2010/9/23 15:33:29字體大。A-A+

      作者:佚名點(diǎn)擊:1322次評(píng)論:0次標(biāo)簽: Proteus

      • 類型:行業(yè)軟件大。1.1M語(yǔ)言:中文 評(píng)分:6.5
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      立即下載

      這篇文章是我的個(gè)人實(shí)踐經(jīng)驗(yàn):

      很多朋友在做Proteus硬件仿真的時(shí)候可能都碰上了仿真速度慢的問(wèn)題,在點(diǎn)擊了開(kāi)始仿真之后,CPU過(guò)載,速度極慢,無(wú)法正常進(jìn)行仿真;Proteus在信息欄提示CPU被使用情況,可能高達(dá)90%到100%,并沒(méi)有按照真實(shí)速度仿真,點(diǎn)擊信息欄中的提示信息就彈出一個(gè)對(duì)話框,說(shuō)是 Simulation is not running in real time due to excessive CPUload,鼠標(biāo)點(diǎn)擊提示,會(huì)展開(kāi)一個(gè)消息框,下面就是消息框內(nèi)的內(nèi)容:

      This message has been generated because the simulation has been unable to keep up with real time for more than 20 consecutive simulation frames. This does not affect the accuracy of the simulation in any way, but it will mean that the simulated system may respond much more slowly to interactive events(e.g. push buttons).
      See Also:

      How to make simulations run faster?

      這里的說(shuō)明中可以看到至少兩個(gè)信息:第一,速度慢并不影響仿真精度;第二,我們可以點(diǎn)擊最下方那句話打開(kāi)另一個(gè)鏈接來(lái)加速仿真;那么,我們就繼續(xù)按照提示來(lái)尋找答案。(也許我們的Proteus版本不同,這些鏈接打開(kāi)順序和方法可能不一樣,我是用的是7.1的版本)點(diǎn)擊 How to make simulations run faster?打開(kāi)Proteus的幫助,進(jìn)入一個(gè)英文界面,我把原文全部貼在這里,之后和你一起解讀。

      ADVANCED TOPICS


      HOW TO MAKE INTERACTIVE SIMULATIONS RUN FASTER


      Introduction


      Although Proteus VSM is able to run many interactive simulations in real

      time, it should be fairly obvious that this cannot be the case for all

      circuits. For example, it is perfectly possible to draw a circuit that will

      oscillate at 1GHz, but there is no way that this can be simulated in real

      time on a computer that may not even execute one machine instruction in 1ns.

      In this section, we will explain in a little more detail what determines the

      complexity of a simulation and how you can optimize a circuit to maximize the

      simulation speed.

      Using Digital Resistor and Diode Models

      First and foremost in this context, it is vital to understand the difference

      between analogue and digital simulation within ProSPICE. This is because the

      simulation of digital circuitry is two or three orders of magnitude (i.e. up

      to 1000 times) faster than the simulation of analogue circuitry. It is for

      this reason that ProSPICE contains a digital simulator at all - that by

      representing the operation of digital components as an event driven process,

      a great deal of unnecessary computation can be avoided.

      For example, whilst a PC with 600MHz P3 processor can simulate around 2

      million digital events per second, the same computer will only be able to

      simulate a sine wave generator running up to about 2kHz before the CPU load

      reaches 100%. Such a waveform will require about 60,000 analogue timepoints

      to be computed per second, and each timepoint will require a convergent

      solution of the circuit nodal equations to be established - a process vastly

      more complex than processing a simple digital event.


      For many components, it should be fairly intuitive as to whether analogue or

      digital simulation will be required. For example, nearly all TTL and CMOS

      parts are represented by digital models, whereas analogue ICs such as op-

      amps, comparators and so forth are represented by analogue models. All

      components which are represented by standard SPICE models require analogue

      simulation.

      However, a grey area arises for components which - though strictly analogue

      in nature - can be represented by a digital model for some purposes. In

      particular, diodes - and perhaps more surprisingly - resistors fall into this

      category. This becomes highly relevant in the context of wire-or logic, pull

      -up resistors, devices with open-collector outputs, and in diode-resistor

      logic networks.


      Example 1 - Wire-Or Logic

      The following circuit section shows a typical wire-or logic network:



      U1:A and U1:B have open-collector outputs and can only sink current. A logic

      1 output level results in a high impedance condition. In terms of DSIM, this

      means that the gate outputs drive either an SLO (strong low) or a FLT

      (floating) logic state. Now if resistor R1 is modelled in the analogue

      domain, PROSPICE must insert a digital to analogue interface object between

      the logic gates and the resistor, and then an analogue to digital interface

      object between the resistor and the input to U2:A. This will result in

      wonderfully detailed simulation of the rise-fall waveforms at this node, and

      the current flow through R1, but will also result in a great deal of

      computation every time the output of U1:A or U1:B changes state.


      All this can be avoided if R1 is modelled digitally. In this case, its

      behaviour is to convert the SHI logic state of VCC to a WHI (weak high) logic

      level. When either NAND gate pulls low, the SLO state overrides the WHI state

      from the resistor and the net state is resolved to be logic low. But when

      neither gate sinks current, the WHI state beats the FLT state and the net

      rises to logic high. All this can be managed within the digital simulation

      paradigm and no analogue simulation is required.


      Therefore, pull up resistors of any kind should almost always be modelled

      digitally.


      Example 2 - Diode-Resistor Logic


      Another case where seemingly analogue circuitry can be modelled in the

      digital domain is diode-resistor networks of the sort shown below. These are

      often found around keypad scanning circuitry where the diodes serve to

      prevent short circuits between the row driving lines if more than more than

      one key is depressed simultaneously.


      As with the wire-or logic example, ProSPICE will quite happily model this in

      the analogue domain but it will be computationally expensive. If a digital

      resistor model is used as above, and a diode is seen as a device which will

      pass only low logic level from cathode to anode and only a high logic level

      from anode to cathode, then the whole network can once again be modelled

      digitally.

      Since keypad scanning routines tend to operate at some speed, and there are

      often numerous diodes and resistors, this is a very important optimization to

      be aware of.


      How to Select the Digital Resistor Model


      1.    Point at the resistor you wish to change and press CTRL-E.

      2.    Click the Edit All Properties as Text checkbox.

      3.    Change the PRIMITIVE property to read


             PRIMITIVE=DIGITAL,RESISTOR


      If you are building a circuit from scratch, and know that you will want a

      particular resistor to be modelled digitally, you can also achieve this by

      picking the PULLUP or PULLDOWN models from the component library. This

      devices already contains the PRIMITIVE property as above.


      How to Select the Digital Diode Model


      1.    Point at the diode you wish to change and press CTRL-E.


      2.    Click the Edit All Properties as Text checkbox.


      3.    Change the PRIMITIVE property to read


             PRIMITIVE=DIGITAL,DIODE


      4.    Delete any MODEL property, as SPICE parameters have no meaning for the

      digital diode model.


      If you are building a circuit from scratch, and know that you will want a

      particular diode to be modelled digitally, you can also achieve this by

      picking the DIODE-DIGITAL device the component library. This device already

      contains the PRIMITIVE property as above.

      Optimizing Memory Accesses to External RAM and ROM

      Many larger microprocessor designs make use of ROM, RAM or EEPROM memory

      devices external to the microcontroller itself. These may store the program

      code, or be used to supplement internal SRAM present within the CPU chip

      itself. Given a correct address decoding circuit, and assuming that the

      memory device is modelled, Proteus VSM will correctly simulate such designs

      as drawn. When the CPU accesses external memory, the model will drive the

      address, data and control lines appropriately, and external decode logic and

      memory model will respond by reading or writing the appropriate locations.

      This is quite useful if you wish to verify that your memory decoding

      circuitry works as designed, but is also extremely expensive in terms of

      computation. Setting up a 16 bit address will create a minimum of 16 digital

      events and reading or writing a byte of data to/from data bus will generate

      another 8. Removing the data from the bus afterwards will create another 8

      events. Where address and data lines are multiplexed, as in the above HC11

      design, even more events will be generated. All this compares very

      unfavourably with the ability of a VSM CPU model to execute an instruction

      using just one event per machine cycle.


      Therefore, we have provided the CPU models with the ability to simulate

      accesses to external memory internally to the model. At the time of writing

      this applies to the 8051,

      HC11 and the larger AVR CPU models. External memory may be declared using

      EXTRAM, or EXTROM properties which specify the memory range for each block of

      external memory. Full details are provided in the model specific help for

      these processors, which you can access from the Edit Component dialogue form,

      or from the Start Menu.


      Once the external memory map has been defined in this way, instructions which

      access external memory within the specified ranges can be simulated without

      generating large numbers of digital events. Accesses to memory mapped

      peripherals can still be fully simulated, since these will lie at locations

      outside the memory ranges specified in the EXTRAM and EXTROM properties.

      這里就列出了所有問(wèn)題的根源了;各位朋友不妨多看看這里的英文幫助,磨刀不誤砍柴

      工,這里的幫助內(nèi)容比任何人的經(jīng)驗(yàn)之談要高明得多;


      好了,讓我來(lái)讀讀這里的幫助,下面是我讀出的基本內(nèi)容之一:

      第一:使用數(shù)字式的電阻和二極管(Using Digital Resistor and Diode Models)

      這句話是我的翻譯,原文的意思是如果把所有的二極管和電阻都看成是模擬量那樣仿真的話,Proteus的速度會(huì)大大下降;所以所有的上拉電阻都可以看成是數(shù)字量的模擬(原文是:Therefore, pull up resistors of any kind should almost always bemodelled digitally.);而一些作為邏輯門(mén)電路用的二極管也可以看成數(shù)字式的;因此,需要對(duì)仿真的元件進(jìn)行設(shè)置。

      1)對(duì)電阻的設(shè)置(How to Select the Digital Resistor Model) How to Select the Digital Resistor Model


      1.    Point at the resistor you wish to change and press CTRL-E.

      2.    Click the Edit All Properties as Text checkbox.

      3.    Change the PRIMITIVE property to read


             PRIMITIVE=DIGITAL,RESISTOR

      2)對(duì)二極管的設(shè)置(How to Select the Digital Diode Model)

      1.    Point at the diode you wish to change and press CTRL-E.

      2.    Click the Edit All Properties as Text checkbox.

      3.    Change the PRIMITIVE property to read

             PRIMITIVE=DIGITAL,DIODE

      4.    Delete any MODEL property, as SPICE parameters have no meaning for thedigital diode model

             另外說(shuō)明,在編輯Properties時(shí),在文本框里鍵入的內(nèi)容若用中括號(hào){}括起來(lái),那么在仿真界面就不會(huì)顯示出來(lái),比如

      {MODFILE=74AND2.MDF}
      {PACKAGE=DIL14}
      {ITFMOD=TTL}

      第二:Optimizing Memory Accesses to External RAM and ROM


      這個(gè)問(wèn)題我還沒(méi)有遇到過(guò),也不太明白其中的內(nèi)容,希望比較熟悉單片機(jī)方面有的朋友做補(bǔ)充了。。

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